This invention relates to integrated circuits and, more specifically, to dual-polysilicon structures in integrated circuits and a method for making them.
Device structures with dual layers of polysilicon over oxide layers of differing thickness have many uses in integrated circuits such as Dynamic Random Access Memory (DRAM) cells, Static Random Access Memory (SRAM) cells, etc. The process for manufacturing dual-polysilicon structures currently requires multiple polysilicon depositions, patterning, and etches. Each deposition, patterning, and etch sequence is both time consuming and costly.
Additionally, the multi-layered polysilicon structure produced by such a known process yields an uneven topology upon which further processing steps must typically be performed. Carrying out further steps on such an uneven topology can be difficult.
The present invention is directed to a new method for fabricating dual-polysilicon structures and integrated circuits. The method uses fewer steps than those used in prior art processes. In accordance with the invention, trenches of differing depths are formed in an insulating layer prior to depositing a polysilicon layer. The trenches are formed by forming a first insulating layer and a barrier layer above the first insulating layer. Subsequently, a second insulating layer is formed above the barrier layer. A first trench is formed in the second insulating layer and a second trench is formed through the first insulating layer, the barrier layer, and the second insulating layer. An implantation barrier is deposited in each trench, and then ion implantation is performed to create self-aligned source and drain regions. Polysilicon, sufficient to fill the trenches, is then deposited and planarized. This process reduces the number of steps required to achieve a dual-polysilicon structure using a single polysilicon formation step. Additionally, the present invention provides a structure that has a more level topography than that provided by prior art methods.